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GTLP16612 18-Bit TTL/GTLP Universal Bus Transceiver
March 1995 Revised March 2001
GTLP16612 18-Bit TTL/GTLP Universal Bus Transceiver
General Description
The GTLP16612 is an 18-bit universal bus transceiver which provides TTL to GTLP signal level translation. The device is designed to provide a high speed interface between cards operating at TTL logic levels and a backplane operating at GTLP logic levels. High speed backplane operation is a direct result of GTLP's reduced output swing (<1V), reduced input threshold levels and output edge rate control which minimizes signal settling times. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3. Fairchild's GTLP has internal edge-rate control and is Process, Voltage, and Temperature (PVT) compensated. Its function is similar to BTL or GTL but with different driver output levels and receiver threshold. GTLP output low voltage is typically less than 0.5V, the output high is 1.5V and the receiver threshold is 1.0V.
Features
s Bidirectional interface between GTLP and TTL logic levels s Designed with an edge rate control circuit to reduce output noise on GTLP port s VREF pin provides external supply reference voltage for receiver threshold adjustability s Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature s TTL compatible Driver and Control inputs s Designed using Fairchild advanced CMOS technology s Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs s Power up/down and power off high impedance for live insertion s 5V tolerant inputs and outputs on LVTTL port s Open drain on GTLP to support wired-or connection s Flow-through pinout optimizes PCB layout s D-type flip-flop, latch and transparent data paths s A Port outputs source/sink
-32 mA/+32 mA
Ordering Code:
Order Number GTLP16612MEA GTLP16612MTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
(c) 2001 Fairchild Semiconductor Corporation
DS012390
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GTLP16612
Pin Descriptions
Pin Names OEAB OEBA CEAB CEBA LEAB LEBA CLKAB CLKBA VREF A1-A18 Description A-to-B Output Enable (Active LOW) B-to-A Output Enable (Active LOW) A-to-B Clock Enable (Active LOW) B-to-A Clock Enable (Active LOW) A-to-B Latch Enable (Transparent HIGH) B-to-A Latch Enable (Transparent HIGH) A-to-B Clock Pulse B-to-A Clock Pulse GTLP Input Reference Voltage A-to-B TTL Data Inputs or B-to-A 3-STATE Outputs B1-B18 B-to-A GTLP Data Inputs or A-to-B Open Drain Outputs
Connection Diagram
Functional Description
The GTLP16612 combines a universal transceiver function with a TTL to GTLP translation. The A Port and control pins operate at LVTTL or 5V TTL levels while the B Port operates at GTLP levels. The transceiver logic includes D-type latches and D-type flip-flops to allow data flow in transparent, latched and clock mode. The functional operation is described in the truth table below.
Truth Table
(Note 1) Inputs CEAB X L L X X L L H OEAB H L L L L L L L LEAB X L L H H L L L CLKAB X H L X X A X X X L H L H X Output B Z B0(Note 2) B0(Note 3) L H L H B0(Note 3) Clocked storage of A data Clock inhibit Latched storage of A data Transparent Mode

X
Note 1: A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, CLKBA, and CEBA. Note 2: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. Note 3: Output level before the indicated steady-state input conditions were established.
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GTLP16612
Logic Diagram
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GTLP16612
Absolute Maximum Ratings(Note 4)
Supply Voltage (VCC, VCCQ) DC Input Voltage (VI) DC Output Voltage (VO) Outputs 3-STATE Outputs Active (Note 5) DC Output Sink Current into A Port IOL DC Output Source Current from A Port IOH DC Output Sink Current into B Port in the LOW State, IOL DC Input Diode Current (IIK) VI < 0V DC Output Diode Current (IOK) VO < 0V VO > VCC Storage Temperature (TSTG) ESD Performance 80 mA 64 mA
-0.5V to +7.0V -0.5V to +7.0V -0.5V to +7.0V -0.5V to VCC + 0.5V
Recommended Operating Conditions (Note 6)
Supply Voltage VCC VCC VCCQ Bus Termination Voltage (VTT) Input Voltage (VI) on A Port and Control Pins HIGH Level Output Current (IOH) A Port LOW Level Output Current (IOL) A Port B Port Operating Temperature (TA) 0.0V to 5.5V 3.15V to 3.45V 4.75V to 5.25V 1.35V to 1.65V
-64 mA
-32 mA +32 mA +34 mA -40C to +85C
-50 mA -50 mA +50 mA -65C to +150C >2000V
Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristic tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 5: IO Absolute Maximum Rating must be observed. Note 6: Unused inputs must be held HIGH or LOW.
DC Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (Unless Otherwise Noted). Symbol VIH VIL VREF VIK VOH A Port VCC = 3.15V, VCCQ = 4.75V VCC, VCCQ = Min to Max (Note 8) VCC = 3.15V VCCQ = 4.75V VOL A Port VCC, VCCQ = Min to Max (Note 8) VCC = 3.15V VCCQ = 4.75V B Port II Control Pins A Port VCC = 3.15V VCCQ = 4.75V VCC, VCCQ = 0 or Max VCC = 3.45V VCCQ = 5.25V B Port IOFF II(hold) IOZH IOZL A Port A Port A Port B Port A Port B Port VCC = 3.45V VCCQ = 5.25V VCC = VCCQ = 0 VCC = 3.15V, VCCQ = 4.75V VCC = 3.45V, VCCQ = 5.25V VCC = 3.45V, VCCQ = 5.25V IOL = 34 mA VI = 5.5V or 0V VI = 5.5V VI = VCC VI = 0 VI = VCCQ VI = 0 VI or VO = 0 to 4.5V VI = 0.8V VI = 2.0V VO = 3.45V VO = 1.5V VO = 0 VO = 0.65V 75 -20 1 5 -20 -10 0.65 10 20 1 -30 5 -5 100 A A A A A A V A II = -18 mA IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 100 A IOL = 32 mA VCC - 0.2 2.4 2.0 0.2 0.5 V V B Port Others B Port Others 1.0 -1.2 Test Conditions Min VREF +0.1 2.0 0.0 VREF -0.1 0.8 Typ (Note 7) VTT Max Units V V V V V
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GTLP16612
DC Electrical Characteristics
Symbol ICCQ (VCCQ) A or B Ports VCC = 3.45V, VCCQ = 5.25V, IO = 0, VI = VCCQ or GND ICC (VCC) A or B Ports VCC = 3.45V, VCCQ = 5.25V, IO = 0, VI = VCCQ or GND ICC (Note 9) A Port and Control Pins VCC = 3.45V, VCCQ = 5.25V, A or Control Inputs at VCC or GND CIN CI/O CI/O Control Pins A Port B Port
(Continued)
Min Typ (Note 7) 30 30 30 0 0 0 0 40 40 40 1 1 1 1 mA mA mA Max
Test Conditions Outputs HIGH Outputs LOW Outputs Disabled Outputs HIGH Outputs LOW Outputs Disabled One Input at 2.7V
Units
VI = VCCQ or 0 VI = VCCQ or 0 VI = VCCQ or 0
8 9 6 pF
Note 7: All typicaI values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25C. Note 8: For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. Note 9: This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
AC Operating Requirements
Over recommended ranges of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted). Symbol fMAX tW Maximum Clock Frequency Pulse Duration LEAB or LEBA HIGH CLKAB or CLKBA HIGH or LOW tS Setup Time A before CLKAB B before CLKBA A before LEAB B before LEBA CEAB before CLKAB CEBA before CLKBA tH Hold Time A after CLKAB B after CLKBA A after LEAB B after LEBA CEAB after CLKAB CEBA after CLKBA Min 150 3.0 ns 3.2 0.5 3.1 1.3 3.7 0.4 1.0 1.5 0.0 0.5 0.0 1.5 1.7 ns ns Max Unit MHz
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GTLP16612
AC Electrical Characteristics
Over recommended range of supply voltage and operating free-air temperature, VREF = 1.0V (unless otherwise noted).
CL = 30 pF for B Port and CL = 50 pF for A Port.
Symbol From (Input) tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tRISE tFALL tPLH tPHL tPLH tPHL tPLH tPHL tPZH, tPZL tPHZ, tPLZ
Note 10: All typical values are at VCC = 3.3V, VCCQ = 5.0V, and TA = 25C.
To (Output) B
Min
Typ (Note 10)
Max
Unit
A
1.0 1.0
4.3 5.0 4.5 5.3 4.6 5.4 4.4 6.1 2.6 2.6
6.5 ns 8.2 6.7 ns 8.6 6.7 ns 8.7 6.2 ns 9.8 ns
LEAB
B
1.8 1.5
CLKAB
B
1.8 1.5
OEAB
B
1.6 1.3
Transition time, B outputs (20% to 80%) Transition time, B outputs (20% to 80%) B A 2.0 1.4 LEBA A 2.1 1.9 CLKBA A 2.3 2.2 OEBA A 1.5 1.9
5.6 5.0 4.2 3.3 4.4 3.5 5.0 3.9
8.2 ns 7.2 6.3 ns 5.0 6.8 ns 5.2 6.2 ns 7.9
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GTLP16612
Test Circuits and Timing Waveforms
Test Circuit for A Outputs Test Circuit for B Outputs
CL includes probes and jig capacitance. CL includes probes and jig capacitance. For B Port outputs, CL = 30 pF is used for worst case edge rate.
Voltage Waveforms Pulse Duration (Vm = 1.5V for A Port and 1.0V for B Port)
Voltage Waveforms Propagation Delay Times (A Port to B Port)
Voltage Waveforms Setup and Hold Times (Vm = 1.5V for A Port and 1.0V for B Port)
Voltage Waveforms Propagation Delay Times (B Port to A Port)
All input pulses have the following characteristics: frequency = 10 MHz, tr = tf = 2 ns, ZO = 50. The outputs are measured one at a time with one transition per measurement. Voltage Waveforms Enable and Disable Times (A Port)
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. All input pulses have the following characteristics: frequency = 10 MHz, tr = tf = 2 ns, ZO = 50. The outputs are measured one at a time with one transition per measurement.
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GTLP16612
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Package Number MS56A
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GTLP16612 18-Bit TTL/GTLP Universal Bus Transceiver
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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